1. Field of the Invention
The present invention relates to a flat display device wherein a storage capacitance element is connected to a thin-film transistor that drives a pixel.
2. Description of the Related Art
FIG. 8 is a plan view showing the structure of a prior-art flat display device 90. The flat display device 90 includes a plurality of liquid crystal portions 9 arranged substantially in a matrix, and a plurality of thin-film transistors (TFTs) 4 that are provided to drive the respective liquid crystal portions 9. Each liquid crystal portion 9 functions as a capacitive load. Each thin-film transistor 4 is an N-channel transistor.
Each thin-film transistor 4 is provided with a gate terminal 5, a source terminal 6 and a drain terminal 7. Each liquid crystal portion 9 is connected to the drain terminal 7 of the associated thin-film transistor 4.
The gate terminals 5 of the respective thin-film transistors 4 are connected to a plurality of gate electrodes 19, respectively, which are disposed to extend in a horizontal direction and spaced from each other at predetermined intervals. The source terminals 6 of the respective thin-film transistors 4 are connected to a plurality of source electrode lines 3, respectively, which are disposed to extend in a vertical direction and spaced from each other at predetermined intervals.
A storage capacitance element 8 is connected to the associated liquid crystal portion 9 and to the drain terminal of the associated thin-film transistor 4 that drives the liquid crystal portion 9. The respective liquid crystal portions 9 are connected via the storage capacitance elements 8 to a plurality of storage capacitance electrodes 91 that are disposed to extend in the horizontal direction and spaced from each other at predetermined intervals. A counter electrode 22 is provided on a side opposite to the thin-film transistors 4, with the associated liquid crystal portion 9 interposed.
A parasitic capacitance 24 exists at an intersection between each source electrode 3 and the associated gate electrode 19. A parasitic capacitance 23 exists at an intersection between each source electrode 3 and the associated storage capacitance electrode 91.
Each source electrode 3 is connected to a source electrode drive circuit 92. Each gate electrode 19 and each storage capacitance electrode 91 are connected to a scan circuit 25.
The operation of the flat display device 90 with the above structure will now be described. FIG. 9 is a waveform diagram for illustrating the operation of the flat display device 90. To begin with, the scan circuit 25 applies compensation voltages 12, 13, 14 and 15 in order to sequentially scan the storage capacitance electrodes 91. Each of the compensation voltages 12, 13, 14 and 15 has three values: a high voltage, a low voltage and an intermediate voltage. When the storage capacitance electrode 91 is not scanned, the intermediate compensation voltage of the three-level compensation voltages is applied to the storage capacitance electrode 91. When the storage capacitance electrode 91 is scanned, the high voltage and low voltage of the three-level compensation voltages are alternately applied in accordance with the polarity of the pixel voltage. In the next frame period 27, the compensation voltage of a polarity opposite to that of the compensation voltage applied in the previous frame period 27 is applied.
Subsequently, in order to turn on the thin-film transistors 4 connected to the same gate electrode 19, the scan circuit 25 sequentially applies gate drive voltages 16, 17 and 18 to the gate electrodes 19. In each of the gate drive voltages 16, 17 and 18, the high level corresponds to a voltage at which the thin-film transistor 4 is turned on. The low level corresponds to a voltage at which the thin-film transistor 4 is turned off. The gate electrodes 19 are sequentially scanned by successively shifting the pulses of the gate drive voltages 16, 17 and 18. In the next frame period 27, the pulses are shifted once again, thereby sequentially scanning the gate electrodes 19.
The source electrode drive circuit 92 applies a video signal voltage 93, which corresponds to an image to be displayed, to each source electrode 3, so as to charge each storage capacitance element 8 and each liquid crystal portion 9 to a desired voltage via the associated thin-film transistor 4. The polarity of the video signal voltage 93 alternately changes for each scan row in an order of plus, minus, plus, . . . . In the next frame period 27, the polarity alternately changes in the order of minus, plus, minus, . . . .
The scan circuit 25 sets the gate drive voltage 16 at the low level in order to turn off the thin-film transistors 4 that are connected to the same gate electrode 19. If each thin-film transistor 4 is turned off, the voltage that is charged in each storage capacitance element 8 and each liquid crystal portion 9 is retained. Subsequently, the scan circuit 25 switches the compensation voltage 12, which is applied to the storage capacitance electrode 91, to an intermediate voltage. Thereby, the compensation voltage is superimposed on the voltage that is retained in each liquid crystal portion 9, and the resultant voltage is retained as a pixel voltage. The pixel voltage is retained until the next scan. In this way, the gate lines are sequentially scanned to perform a display for the entire frame.
Upon completion of the scan for one frame, the voltage polarities of the video signal voltage and compensation voltage are reversed for AC-driving of the liquid crystal in which the polarity of the voltage retained as the pixel voltage alternately changes, and then the scan is executed again.
In general, in order to suppress flicker on a display screen, the polarity of the voltage retained as the pixel voltage is reversed on a line-by-line basis. This method is generally called “line-reversal driving.”
FIG. 10A is a diagram for explaining the polarity of the pixel application voltage that is applied in odd-number frames, and FIG. 10B is a diagram for explaining the polarity of the pixel application voltage that is applied in even-number frames. Each block indicates the polarity of pixel voltage of each pixel by “+” or “−”. The row direction is a scan direction. In the prior-art flat display device, the polarities of the pixel voltages are equal in each row, and are different from row to row. In addition, the polarity of the voltage applied to each pixel is made different between an odd-number frame and an even-number frame, thereby AC-driving the liquid crystal.
Pixel application voltages 95, 96 and 97 having the shown waveforms are voltages applied to the liquid crystal portions that form the pixels. To begin with, a low-level compensation voltage 12 is applied to the storage capacitance electrode 91. Thereafter, when a high-level gate drive voltage 16 is applied to the gate electrode 19, the liquid crystal portion is charged with the video signal voltage 93 that is applied to the source electrode 3. Subsequently, a low-level gate drive voltage 16 is applied to the gate electrode 19 and the video signal voltage 93, which is applied to the source electrode 3, is retained by the liquid crystal portion.
Then, an intermediate-level compensation voltage 12 is applied to the storage capacitance electrode 91. Thereby, a difference voltage corresponding to a variation in the compensation voltage is superimposed on the previously retained video signal voltage, and the resultant voltage is applied to the liquid crystal portion and retained as the pixel application voltage 95.
In the next frame period 27, the video signal voltage 93 and compensation voltage 12 of different polarities are applied. Thereby, the pixel application voltage 95 of a different polarity is applied for each frame period 27 to attain AC-driving of the liquid crystal. In addition, the video signal voltage and compensation voltage of different polarities are applied for each row, thereby improving the problem of flicker.
With an increase in screen size and definition of the flat display device, a parasitic capacitance at an intersection between the source electrode and the gate electrode and a parasitic capacitance at an intersection between the source electrode and the storage capacitance electrode will increase. Moreover, wiring resistance of the source electrode, gate electrode and storage capacitance electrode will increase. Consequently, the charging time-constant of the source electrode, gate electrode and storage capacitance electrode increases, and a problem arises in that transition delay and distortion increases in the drive waveform. In particular, a remarkable increase occurs in the parasitic capacitance at the intersection between the source electrode and the storage capacitance electrode, and in the charging time-constant due to an increase in wiring resistance.
In the conventional method of driving the flat display device wherein charging for each row is executed by the video signal voltages whose polarities are changed simultaneously, the currents for charging or discharging the storage capacitance elements of the pixels for each row and the parasitic capacitances at the intersections between the source electrodes and the storage capacitance electrode simultaneously flow via the storage capacitance electrode at the time of scan. Since the storage capacitance electrode has a high wiring resistance, the currents cannot sufficiently flow, and the charging time-constant increases. Thus, transition delay in drive waveform occurs. As a result, a problem arises in that the liquid crystal portion cannot be charged with a desired pixel voltage.
Besides, even at the time of no scan, the currents for charging or discharging the parasitic capacitances at the intersections between the source electrodes and the storage capacitance electrode simultaneously flow in accordance with the video signal voltages whose polarities are simultaneously changed on a row-by-row basis. Consequently, the storage capacitance electrode, which has a high wiring resistance, cannot cause such currents to fully flow, and the charging time-constant increases. Thus, distortion in drive waveform occurs. As a result, a problem arises in that the liquid crystal portion cannot be charged with a desired pixel voltage.
Consequently, the prior-art flat display device has a problem that non-uniformity called “crosstalk” occurs laterally in a displayed image and considerably deteriorates the display quality.
The present invention has been made in order to solve the above problem, and the object of the invention is to provide a flat display device having a uniform, good display quality.    [Patent Document 1]    Jpn. Pat. Appln. KOKAI Publication No. 4-52684    [Patent Document 2]    Jpn. Pat. Appln. KOKAI Publication No. 2002-140043